Study on Nanocrystal Nonvolatile Memory Devices

碩士 === 國立交通大學 === 電子工程系所 === 92 === In a conventional nonvolatile memory, charge is stored in a polysilicon floating gate (FG) surrounded by dielectrics. The scaling limitation stems from the requirement of very thin tunnel oxide layer. For FG, once the tunnel oxide develops a leaky path under repea...

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Bibliographic Details
Main Authors: Sheng Hung Lin, 林泩宏
Other Authors: Simon M. Sze
Format: Others
Language:en_US
Published: 2004
Online Access:http://ndltd.ncl.edu.tw/handle/x8n365
Description
Summary:碩士 === 國立交通大學 === 電子工程系所 === 92 === In a conventional nonvolatile memory, charge is stored in a polysilicon floating gate (FG) surrounded by dielectrics. The scaling limitation stems from the requirement of very thin tunnel oxide layer. For FG, once the tunnel oxide develops a leaky path under repeated write/erase operation, all the stored charge will be lost. Therefore, the thickness of the tunnel oxide can not be scaled down to about 7 nm. To alleviate the scaling limitation of the conventional FG device while preserving the fundamental operating principle of the memory, we have studied the distributed charge storage approach such as the nanocrystal nonvolatile memory. Each nanodot will typically store only a handful of electrons; collectively the charges stored in these dots control the channel conductivity of the memory device. Nanocrystal charge storage offers several advantages, the main one being the potential to use thinner tunnel oxide without sacrificing nonvolatility. This is a quite attractive proposition since reducing the tunnel oxide thickness is a key to lowering operating voltages and/or increasing operating speeds. The improved scalability results not only from the distributed nature of the charge storage, which makes the storage more robust and fault-tolerant, but also from the beneficial effects of Coulomb blockade. A local leaky path will not cause a fatal loss of information for the nanocrystal nonvolatile memory device. Also, the nanocrystal memory device can maintain good retention characteristics and lower the power consumption. We have fabricated a nonvolatile memory device embedded with Ge nanocrystals by a thermal oxidation of Si0.8Ge0.2 combined with a rapid thermal annealing process. The tunnel oxide in the nonvolatile memory is 4.5 nm-thick and with 5.5-nm Ge nanocrystals reside on it. A low operating voltage, 5V, is implemented and a significant threshold-voltage shift, 0.42V, is observed. Also, we have demonstrated the novel distributed charge storage with GeO2 nano-dots. The mean size and aerial density of the dots are estimated to be about 5.5 nm and 4.3×1011 cm-2, respectively. The composition of the GeO2 dots is confirmed by the XANES measurements. In electrical analyses, a significant memory effect is observed with a threshold voltage shift of 0.45V under 5-V operation. Also, a physical model is proposed to explain the charge storage via the interfacial traps of GeO2 nano-dots. We have also proposed a simple process to fabricate metal nanocrystal memory which is one of the candidates that have great potential of achieving fast write/erase and long retention time simultaneously. Once the self-assembled nanocrystals have controllable density and size distribution, the metal nanocrystals can be incorporated into a standard MOSFET structure to fabricate nonvolatile memory devices.