Low-Power Memory-Based VLC Decoder Designs
碩士 === 國立交通大學 === 電子工程系所 === 92 === In this dissertation, the algorithm and architecture of low-power memory-based VLC decoder designs are presented. Systematic optimization procedures are proposed to reduce the power consumption and maintain the same operation throughputs as the conventional design...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/a96h35 |