A Formal Approach for Interface Compliance Verification in SoC
碩士 === 國立交通大學 === 電子工程系所 === 92 === Verifying whether a building block conforms to certain interface protocol is one of the important steps while constructing a system-on-a-chip (SoC). However, most existing methods have their own limitations. Simulation-based methods have the false positive probl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/j2k7g5 |