The Design and Analysis of a CMOS 8bit 40MS/s Pipelined Analog-to-Digital Converter
碩士 === 國立交通大學 === 電子工程系所 === 92 === In this thesis, the advantage and the architecture of the pipelined analog-to-digital converter (ADC) is described. Furthermore, the error source of the pipelined ADC is shown and discussed. And there are some solutions to these problems in this thesis. We also...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/5qz22g |