Design and Implementation of CMOS Frequency Synthesizer for IEEE 802.11a WLAN
碩士 === 國立交通大學 === 電子工程系所 === 92 === A 5-GHz IEEE 802.11a frequency synthesizer has been fabricated in UMC 0.18-μm CMOS technology. The frequency synthesizer architecture is based on a charge-pump phase-locked loop. To perform frequency synthesis, the synthesizer utilizes the integer-N architecture....
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19129445844142572968 |