New ESD Protection Devices with Dummy-Gate Structure in a Fully-Salicided CMOS Technology
碩士 === 國立交通大學 === 電機資訊學院碩士在職專班 === 92 === Salicidation is one of the key processes for high performance quarter-micron CMOS devices. However, several problems occur when salicide technology is implemented in ESD protection NMOS transistors. The most difficult problem is the low ESD robustness of out...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/49955070652046800225 |