On Debugging Assistance in Assertion-Based Verification
碩士 === 國立中央大學 === 電機工程研究所 === 92 === Abstract In the verification process, debugging is also a hard and time-consuming process and is often done by designers themselves. Because most design errors occur in the early design stages, there are also some approaches proposed for debugging HDL design...
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/21648883650804644604 |