Peak Power Optimization with Compiler Techniques
碩士 === 國立東華大學 === 資訊工程學系 === 92 === In this thesis, we propose a low power instruction scheduling algorithm with a pee-hole peak power limit. The pee-hole peak power optimization algorithm is based on ILP formulation. Given two pee-hole parameters t and w, where t is the pee-hole peak power limi...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/52233114967250146304 |