High Performance PLL Design with BIST Structure for SOC Applications
碩士 === 國立東華大學 === 電機工程學系 === 92 === An effective built-in self-test (BIST) structure of a phase-locked loop (PLL) in digital applications is presented in this work. The proposed BIST structure can identify possible faults in any block such as the phase-detector, charge-pump, loop-filter, voltage-con...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/36579343439014736289 |