Low Power Current-Mode Pipelined Analog-to-Digital Converter Using Regulated Cascode Circuit
碩士 === 國立東華大學 === 電機工程學系 === 92 === The design of a low power current-mode analog-to-digital converter (ADC) is proposed in this thesis. This ADC used a pipelined 1.5-bit/stage architecture with 9 stages, and it contains last 1-bit/stage. The digital error correction circuit is embedded into the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/75385486764773423955 |