Test Planning and Integration of Core-Based System-on-Chip with Multiple Heterogeneous Memories
博士 === 國立清華大學 === 電機工程學系 === 92 === IPs and memory cores are two key components in system-on-chip (SOC). The reuse of IP cores results in test integration challenges. In addition, the usage of mass heterogeneous memory cores in SOC also increases the cost of memory testing. These two issues make the...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15401607035249289474 |