A Layout Analysis Tool For Bridging Defect Modeling In A Logic IC
碩士 === 國立清華大學 === 電機工程學系 === 92 === The stuck-at fault model is popular due to its simplicity, and because it has proven to be effective both in providing high defect coverage when used as a fault model for test generation and when diagnosing a limited range of faulty behaviors. Our method uses the...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/85191182714882375130 |