The Design of a High Speed Pipelined Analog-to-Digital Converter
碩士 === 國立臺灣海洋大學 === 電機工程學系 === 92 === In this thesis, a 8-bit, 80MHz sampling rate CMOS seven-stage pipelined analog-to-digital converter is designed with TSMC 0.35um 2p4m COMS process. The ADC consists of six 1.5-bit stages and the final stage is a 2-bit stage. Digital correction is used to relax t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99148419269767958061 |