Implementations of Bus Functional Models for the PCI Express System
碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === With rapid increase in CPU’s speed, inter-chip bus connection becomes the bottlenecks of computing systems. The problem lies on clock skew since the shared bus protocol needs a synchronous clock control. To break the performance limit of PCI/PCI-X, PCI-SIG defin...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/18340124392124079154 |