| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === With rapid increase in CPU’s speed, inter-chip bus connection becomes the bottlenecks of computing systems. The problem lies on clock skew since the shared bus protocol needs a synchronous clock control. To break the performance limit of PCI/PCI-X, PCI-SIG defines PCI Express, an industry specification for serial connection rather than the original parallel connection. PCI Express is similar to a network protocol. It is a peer to peer, packet based and layered protocol. The PCI Express can provide more bandwidth than PCI/PCI-X bus. Furthermore it is designed to preserve the software/driver interface of earlier PCI version. So in the future, we could see that many chips need to be designed for new applications.
To reduce the design schedule of PCI Express system, a set of Bus Function Models (BFM) are provided. In the thesis, we use Verilog with Verification Language Extension (VLE) toolkits to model the behavior of PCI Express elements. All the BFMs contain all the functionalities defined in the specification. Using the BFMs, we could construct all topologies of PCI Express system. The BFMs are also configurable and programmable. So, they could be easily integrated into the system-level verification environment. It could help designers to reduce the time for verification and improve their productivity.
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