IC HTOL Stress Condition Optimization
碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === HTOL (High Temperature Operation Life) test is used to determine the effects of bias and temperature stress conditions on solid-state devices over time. It simulates the devices’ operating condition in an accelerated manner, and is primarily for device reliabili...
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ndltd-TW-092NTU004281002015-10-13T13:27:34Z http://ndltd.ncl.edu.tw/handle/54997796537677659963 IC HTOL Stress Condition Optimization 積體電路高溫工作生命週期測試條件最佳化 Brian Peng 彭志偉 碩士 國立臺灣大學 電子工程學研究所 92 HTOL (High Temperature Operation Life) test is used to determine the effects of bias and temperature stress conditions on solid-state devices over time. It simulates the devices’ operating condition in an accelerated manner, and is primarily for device reliability evaluation. This paper addresses an SA (Simulated Annealing) method used for the HTOL test stress condition decision-making that is an optimization problem. The goal is to reduce the resources for the HTOL test, hardware or time, under reliability constraints. The theory of reliability statistic model and the SA algorithm are presented. In our optimization algorithm, we need to calculate the accurate HTOL stressed power for the next optimization loop since the Vs (Stressed Voltage) that is optimized will affect not only Afv (Voltage Acceleration Factor) but also Aft (Thermal Acceleration Factor). A curve-fitting algorithm is applied to get reasonable accelerated factors and reliability calculations. The model selection process and statistical analysis of fitted data by different models are also presented. Experimental results with different stress condition priorities and different user settings are given to demonstrate the effectiveness of our approach. Sy-Yen Kuo 郭斯彥 2004 學位論文 ; thesis 73 en_US |
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碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === HTOL (High Temperature Operation Life) test is used to determine the effects of bias and temperature stress conditions on solid-state devices over time. It simulates the devices’ operating condition in an accelerated manner, and is primarily for device reliability evaluation. This paper addresses an SA (Simulated Annealing) method used for the HTOL test stress condition decision-making that is an optimization problem. The goal is to reduce the resources for the HTOL test, hardware or time, under reliability constraints. The theory of reliability statistic model and the SA algorithm are presented. In our optimization algorithm, we need to calculate the accurate HTOL stressed power for the next optimization loop since the Vs (Stressed Voltage) that is optimized will affect not only Afv (Voltage Acceleration Factor) but also Aft (Thermal Acceleration Factor). A curve-fitting algorithm is applied to get reasonable accelerated factors and reliability calculations. The model selection process and statistical analysis of fitted data by different models are also presented. Experimental results with different stress condition priorities and different user settings are given to demonstrate the effectiveness of our approach.
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Sy-Yen Kuo |
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Sy-Yen Kuo Brian Peng 彭志偉 |
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Brian Peng 彭志偉 |
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Brian Peng 彭志偉 IC HTOL Stress Condition Optimization |
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Brian Peng |
title |
IC HTOL Stress Condition Optimization |
title_short |
IC HTOL Stress Condition Optimization |
title_full |
IC HTOL Stress Condition Optimization |
title_fullStr |
IC HTOL Stress Condition Optimization |
title_full_unstemmed |
IC HTOL Stress Condition Optimization |
title_sort |
ic htol stress condition optimization |
publishDate |
2004 |
url |
http://ndltd.ncl.edu.tw/handle/54997796537677659963 |
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