The design of the timing generator with digital control quantized delay locked loop in automatic test equipment
碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === Abstract In this thesis, several architectures of timing generator and delay locked loop are introduced. In timing generator design, it is hard to fulfill high resolution, wide programmable delay range and intrinsic delay at the same time. We proposed a mixed...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45052765174513324428 |