Study on a High Performance Module in Baseband Communication Chips
碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === In this thesis we present a new delay line circuit design. The structure of delay line we adopt in our design is ring counter based delay line, which consists of a ring counter and a latch array. The ring counter works as an address decoder and the latch array i...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/88399283662502212637 |