Microprocessor Testability Analysis for Software-Based Self-Testing

• Main Authors: Chin-Yu Chang, 張欽俞
• Other Authors: 黃俊郎
• Format: Others
• Language: en_US
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/s5g8wy

碩士 === 國立臺灣大學 === 電子工程學研究所 === 92 === Software-Based Self-Testing is a very cost efficient test method. There is no DFT overhead and it achieves at-speed testing without expensive ATE test equipment. However, there are still many bottlenecks. For example, how to generate a high fault coverage test programs? On the other hand, How to synthesize an effective assembly test programs very fast? It is also a big challenge In this paper, we propose a statistical simulation-based approach. At first, a random sequence test template set based on the instruction set architecture of processor is generated. Then the processor is asked to execute by an X-Based simulator. The purpose of X-Based simulation is to extract the relationship between instruction set and modules. According to the simulation result, the statistical method is applied. It guides the test template set to detect internal faults with higher testability. In this approach, the processor is applied under normal functional mode so that processor deeply executes at-speed test without DFT overhead. A real case for 8051 microprocessor is implemented in this paper.