Application on Silicon Wafer Grinding Process Performance Enhancement

• Main Authors: Chi-Hsu Tu, 凃岐旭
• Other Authors: Hong-Tsu Young
• Format: Others
• Language: zh-TW
• Published: 2004
• Online Access: http://ndltd.ncl.edu.tw/handle/53314783598268155061

碩士 === 國立臺灣大學 === 機械工程學研究所 === 92 === Grinding has gained important status in the IC packaging , wafer manufacture and wafer reclaim industry. Grinding process could reach low TTV (Total Thickness Variation) , excellent surface roughness , rapid material removal rate , reduced cycle time and higher automation level. To avoid deep subsurface damage layer and reduce warpage caused by residual stress , assessment should be made prior to production run for the industry. This study will concentrate on grinding 8 inches silicon wafers , and three stages were planned. First , ductile regime grinding and cross-section method are introduced to investigate the subsurface damage layer and critical depth of cut , under the influence of grinding parameters and wheel types. Second , measurement of grinding temperature between grinding wheel and wafer surface device is made. With the relation between warp and grinding temperature established from first step , grinding parameters and suitable surfactant in the cooling water will drop the interface temperature and , hence , leading to lower warp . Third , front side etching and Stoney’s formula will be used to calculate the residual stress and attempt is made to forecast the subsurface damage layer depth.