Design of A 1.5V Low Power Consumption 5.2 GHz CMOS Frequency Synthesizer
碩士 === 聖約翰技術學院 === 自動化及機電整合研究所 === 92 === In this thesis, a frequency synthesizer with low power consumption 16.5mW is designed for wireless communication. This synthesizer is implemented in the TSMC 0.18 um 1P6M Triple Well technology, with operating voltage 1.5 volts, and the output frequency rang...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19527293530322807339 |