Design and Implementation of a Cascaded Converter with Synchronous Rectification
碩士 === 國立臺北科技大學 === 電機工程系碩士班 === 92 === The objective of this thesis is to design and implement a push-pull cascaded buck converter with synchronous rectifier. The converter consists of two stages. The front stage operates under open loop condition to give DC output as the input of the second stage....
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/02451494259943277356 |