New Power Saving Design for CMOS Flash ADC
碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 92 === The flash ADC based on OPA comparators that has the advantage with very high conversion speed (>500MHz), but its chip area is presented 2N that is always larger than other ADC structures, where N is the resolution. This is quite surprising for an N-bit fl...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/87616033352927450334 |