IC design of a new low-power turbo decoder
碩士 === 國立臺北科技大學 === 電腦通訊與控制研究所 === 92 === In this thesis, we propose a new VLSI architecture for low-power turbo decoder. This architecture includes two parts to improve power dissipation properties. Firstly, we develop a new architecture for the soft-in-soft-out decoder which decreases the state st...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/88091083895425401882 |