| Summary: | 碩士 === 淡江大學 === 電機工程學系 === 92 === Because of the great improvement of VLSI technology in recent years, the number of transistors on a sole chip become more and more, and the area of chip actually are smaller and smaller. It causes a tendency to design a system on a chip (SOC). The SOC contain wireless communication, networking and consumer electric…and so on, overall system can be implemented on a single Si chip. Because the system itself is so huge and complex, we need a good design environment to help us to develop the application of hardware and software, like Electronic Design Automation and Test (EDA&T) tool or Hardware-Software Co-design tool. If we use the traditional method and process to design a SOC, which contain the establishment of hardware architecture、logic design and synthesis and circuit layout, it is nearly impossible to finish the process of SOC which can conform to the market demand in the short time (time-to-market). Therefore, in order to obtain and design the more values of SOC part to reduce time-to-market, the reuse of intellectual properties is a indispensable way to speed up the design flow of SOC. In other words, we effectively sort and classify these IP obtained from IP vendor or designed by us to be a cell library. When we need to construct a SOC, we only choose the appropriate IP again from our cell library to perform the design. The above way which called core-based SOC design can reduce the chip design time and accelerate the time-to-market to strive for the biggest market benefit. But as a result of the complexity of SOC, the SOC testing will be more and more difficult and the excessively long testing time also will reduce the SOC competitive ability. Therefore, how to reduce the total design and testing time is an important issue.
The SOC testing time is decided by test architecture (Test Access Mechanism, TAM)、test access width (TAM width) and test schedule. Although the large TAM width can supply a large number of test vector (test pattern) to the core under test to reduce the testing time, but too large TAM width also cause the hardware overhead to decrease the yield of chip and influence the whole system performance. Therefore, a good test design will trade off between the total testing time and the hardware overhead, and try to get the best results in total testing time. Next, the different arrangement of core test schedule will also cause an effect to the SOC total testing time. Moreover, the TAM architecture also directly affect the design of test schedule in the constraint of TAM width,test resource and power consumption. How to adopt the appropriate TAM architecture and design the most effective test schedule to obtain the minimum SOC testing time is this paper will discuss about.
In this paper, we propose a heuristic algorithm to effectively design the test infrastructure to minimize the total test application time under the constraint of available SOC pins. The algorithm efficiently determines the number of TAMs, the width of each TAM, and the assignment of core to TAM to derive the optimal TestRail architecture. We develop this algorithm with the respect of 2-D Rectangle Bin-packing Model and cluster-based algorithm. Our propose algorithm compared to previously ILP based methods can obtain less testing time and computing time. The algorithm proposed by this paper can apply on EDA/CAD tool, and provide SOC designer a fast and effective SOC test schedule solution. It can help designer to optimize test resource to reduce the total testing time and speed up the design and test flow of SOC.
|
|---|
