THE DESIGN OF PLL-BASED FREQUENCY SYNTHESIZER AND CLOCK/DATA RECOVERY CIRCUIT
碩士 === 大同大學 === 電機工程學系(所) === 92 === Based on the phase-locked-loop (PLL) design concepts, this thesis presented the designs of a RF frequency synthesizer with a LC-tank voltage-controlled oscillator and a clock and data recovery (CDR) circuit with a ring oscillator. The implementation of the freque...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/95557622388255585866 |