| Summary: | 博士 === 長庚大學 === 電機工程研究所 === 93 === Negative wordline bias scheme has been adapted in deep submicron to reduce the subthreshold leakage of deep submicron DRAM cell tran-sistors. With excessive negative wordline bias, gate induced drain leakage (GIDL) could dominate cell leakage and degrade product retention time performance. Furthermore, GIDL degrades data retention reliability per-formance even in the standard DRAM backend test. The optimization point of negative wordline bias and subthreshold leakage is discussed in the thesis. Leakage paths of buried strap trench cell are also reviewed in the thesis. The surface doping of the substrate strongly affects the electri-cal field of a cell transistor with NWLB at low voltage regime. Hence, the cell transistors Vt cannot be raised simply by increasing the dose of Vt adjustment implant or arsenic implanted shallow junction. Reliability of data retention is one of the major issues in DRAM. Electrical measure-ment and device simulation show that a trap-assisted leakage degrades the retention time even in packaging process at about 250℃. Simulation re-sults show that a single trap move from a small field region to a high field region, leakage current is increased by one order of magnitude in a cell transistor. It is proposed in this thesis that silicon hydrogen (Si-H) bond-ing of passivation films could modulate the data retention. An optimiza-tion of passivation films to improve data retention reliability is studied in this work.
For future work, Vertical transistor, and recessed channel array tran-sistor are proposed to shrink DRAM cell into nanometer regime.
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