BRICKing: A Two-Step Layout Placement Procedure for Performance Trimming by Using Spatial Correlation Analysis
碩士 === 中華大學 === 電機工程學系碩士班 === 93 === At the time of circuit simulation, transistor parameter make change on the manufacture can't be ignored. General MOS layout placement is accumulated by experience. But by our placement step that does quantitative analysis. This is an important argument that...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/86156725836662705988 |