Low Power and Zero Skew Clock Tree Design with Multiple Voltages
碩士 === 中原大學 === 資訊工程研究所 === 93 === With the number of transistor in an IC increases quickly, the power consumption of the clock tree accounts for 20~50% [4] of the total power consumption in an IC, therefore, the way to effectively reduce the power consumption of the clock tree is certainly require...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/32786484520892792253 |