Low Power and Zero Skew Clock Tree Design with Multiple Voltages

• Main Authors: Ju-De Wu, 吳俊德
• Other Authors: Mely Chen
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/32786484520892792253

碩士 === 中原大學 === 資訊工程研究所 === 93 === 　With the number of transistor in an IC increases quickly, the power consumption of the clock tree accounts for 20~50% [4] of the total power consumption in an IC, therefore, the way to effectively reduce the power consumption of the clock tree is certainly required. Besides, recent IC designs have already been tend to the use the multiple voltages for designs, under this reason, we want to design an algorithm to construct clock tree to conform to the low power and zero-skew requirements. In this paper, we design a low power and zero-skew clock tree. After cells in the circuit are placed, we apply the location of flip-flops and the information of the multiple voltages to DME routing algorithm to synthesize the clock tree. During the constructing clock tree, we reduce the power consumption of the clock tree by adding clocked gates. In this paper, we use the bottom-up approach to construct the topology of clock tree. In top-down process, we route the clock tree according to the topology of the tree. At the end, after inserting the level converters, we adjust the length of the branches to form a zero-skew clock tree. We apply the circuits in references [19] and the benchmark of ISCAS’89 [20] into our method to construct the clock tree. The experimental results show that comparing to the method of constructing multiple single-voltage clock trees, our method can average reduce the power consumption of these two set of circuits by 22.9% and 21.94% respectively.