Study of Strain Engineering for Nano-scale CMOS devices process
碩士 === 中原大學 === 電子工程研究所 === 93 === Abstract This paper reports the local process stress and the global process stress for CMOS devices. Both process and device simulations for the local process stress are simulated by FLOOPS-ISE™ and DESSIS-ISE™. The simulated process is similar to the 90 nm technol...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/96666470805106498721 |