| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 93 === Nowadays, most communication systems employed digital filters. Among many kinds of filters, FIR filter is much easier to be controlled than others. However, the drawback of the FIR filter is that the latency is too long. The latency is a main weakness in an FIR design. Many designers hope that the latency can be shortened. Therefore, the IIR filter is gradually adopted because it has much shorter latency. However, the zero point of the IIR filter is close to the unit circle. Thus, the control character of IIR is discrete instead of convergent. This thesis is aimed to design a parameter adjustable IIR filter. It reduces the latency of the IIR filter to be 21 clock cycles for the five tiers filter. This filter can be combined with DSP or RISC to be a whole IP of SOC or ASIC so that the entire system is more efficient.
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