An Asynchronous Design for Modular Multiplication
碩士 === 輔仁大學 === 電子工程學系 === 93 === Modular multiplication is a major computation in RSA cryptograph systems and residue number systems. To achieve fast computation, various VLSI implementations for modular multiplication have been proposed. Most of them are synchronous designs. The rapid progress in...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/02729387000957680850 |