An Asynchronous Design for Modular Multiplication

• Main Authors: Huei-Tsung Wu, 吳輝宗
• Other Authors: Kuan-Jen Lin
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/02729387000957680850

碩士 === 輔仁大學 === 電子工程學系 === 93 === Modular multiplication is a major computation in RSA cryptograph systems and residue number systems. To achieve fast computation, various VLSI implementations for modular multiplication have been proposed. Most of them are synchronous designs. The rapid progress in semiconductor technology leads to denser and faster synchronous circuits. [1] However, the clock skew problem and high peak power consumption at clock become very serious. Asynchronous circuits that do not use clocks feature the advantages of clock-skew-freeness as well as low peak power as compared to the synchronous ones. In this thesis, we propose an asynchronous modular multiplication design using multiple delay-lines scheme. The scheme not only uses single-rail data paths, but also allows early completion. This means it can usually work in average-case delay, rather than in worst-case delay. Through data possibility analysis, performance improvements of up to 23.58% over a comparable synchronous design are expected. The design was implemented with the UMC 0.18um technology. The experimental results show the effectiveness of our design.