On-Chip and Inter-Chip Bidirectional Transceivers
碩士 === 輔仁大學 === 電子工程學系 === 93 === As the VLSI process is scaled down, a single IC possibly contains an entire system (system-on- chip (SOC)). As the device size scaled down, Gate delay is reduced. The interconnection width is so narrow that the delay of the interconnection becomes larger. Therefore,...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99279752450182947588 |