| Summary: | 碩士 === 輔仁大學 === 電子工程學系 === 93 === As the VLSI process is scaled down, a single IC possibly contains an entire system (system-on- chip (SOC)). As the device size scaled down, Gate delay is reduced. The interconnection width is so narrow that the delay of the interconnection becomes larger. Therefore, the interconnect delay dominants the global chip delay in very deep sub-micron era. Various methods of reducing the interconnect delay have been investigated. One of them is to use the material of the interconnection copper and lower dielectric constant to reduce the resistance and capacitance. The others are to use special receivers for the reduction of long interconnection RC delay.
In this thesis, we propose several new circuits.
1. Drain-Switch-Current-Source (DSCS)
2. Self-Bias-Current-Source (SBCS)
3. Gate-Switch-Current-Source (GSCS)
4. Diode-Connected-Current-Source (DCCS)
5. Switch-Bias-Current-Source (SWBCSN)
6. Switch-Bias-Current-Source (SWBCSP)
7. Gate-Switch with Terminator-Resistor (GSTRN)
8. Gate-Switch with Terminator-Resistor (GSTRP)
In this thesis, in addition to the simulation of the proposed circuits, and one test chip using TSMC 0.18μm 1P6M process with experimental circuits are designed and measured to verify the speed performance of the long interconnection design.
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