On-Chip and Inter-Chip Bidirectional Transceivers
碩士 === 輔仁大學 === 電子工程學系 === 93 === As the VLSI process is scaled down, a single IC possibly contains an entire system (system-on- chip (SOC)). As the device size scaled down, Gate delay is reduced. The interconnection width is so narrow that the delay of the interconnection becomes larger. Therefore,...
| Main Authors: | , |
|---|---|
| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
|
| Online Access: | http://ndltd.ncl.edu.tw/handle/99279752450182947588 |
| id |
ndltd-TW-093FJU00428033 |
|---|---|
| record_format |
oai_dc |
| spelling |
ndltd-TW-093FJU004280332016-06-08T04:13:37Z http://ndltd.ncl.edu.tw/handle/99279752450182947588 On-Chip and Inter-Chip Bidirectional Transceivers 晶片上和晶片間雙向傳輸接收器 Ching-Chieh Wu 吳慶傑 碩士 輔仁大學 電子工程學系 93 As the VLSI process is scaled down, a single IC possibly contains an entire system (system-on- chip (SOC)). As the device size scaled down, Gate delay is reduced. The interconnection width is so narrow that the delay of the interconnection becomes larger. Therefore, the interconnect delay dominants the global chip delay in very deep sub-micron era. Various methods of reducing the interconnect delay have been investigated. One of them is to use the material of the interconnection copper and lower dielectric constant to reduce the resistance and capacitance. The others are to use special receivers for the reduction of long interconnection RC delay. In this thesis, we propose several new circuits. 1. Drain-Switch-Current-Source (DSCS) 2. Self-Bias-Current-Source (SBCS) 3. Gate-Switch-Current-Source (GSCS) 4. Diode-Connected-Current-Source (DCCS) 5. Switch-Bias-Current-Source (SWBCSN) 6. Switch-Bias-Current-Source (SWBCSP) 7. Gate-Switch with Terminator-Resistor (GSTRN) 8. Gate-Switch with Terminator-Resistor (GSTRP) In this thesis, in addition to the simulation of the proposed circuits, and one test chip using TSMC 0.18μm 1P6M process with experimental circuits are designed and measured to verify the speed performance of the long interconnection design. Hong-Yi Huang 黃弘一 2005 學位論文 ; thesis 94 zh-TW |
| collection |
NDLTD |
| language |
zh-TW |
| format |
Others
|
| sources |
NDLTD |
| description |
碩士 === 輔仁大學 === 電子工程學系 === 93 === As the VLSI process is scaled down, a single IC possibly contains an entire system (system-on- chip (SOC)). As the device size scaled down, Gate delay is reduced. The interconnection width is so narrow that the delay of the interconnection becomes larger. Therefore, the interconnect delay dominants the global chip delay in very deep sub-micron era. Various methods of reducing the interconnect delay have been investigated. One of them is to use the material of the interconnection copper and lower dielectric constant to reduce the resistance and capacitance. The others are to use special receivers for the reduction of long interconnection RC delay.
In this thesis, we propose several new circuits.
1. Drain-Switch-Current-Source (DSCS)
2. Self-Bias-Current-Source (SBCS)
3. Gate-Switch-Current-Source (GSCS)
4. Diode-Connected-Current-Source (DCCS)
5. Switch-Bias-Current-Source (SWBCSN)
6. Switch-Bias-Current-Source (SWBCSP)
7. Gate-Switch with Terminator-Resistor (GSTRN)
8. Gate-Switch with Terminator-Resistor (GSTRP)
In this thesis, in addition to the simulation of the proposed circuits, and one test chip using TSMC 0.18μm 1P6M process with experimental circuits are designed and measured to verify the speed performance of the long interconnection design.
|
| author2 |
Hong-Yi Huang |
| author_facet |
Hong-Yi Huang Ching-Chieh Wu 吳慶傑 |
| author |
Ching-Chieh Wu 吳慶傑 |
| spellingShingle |
Ching-Chieh Wu 吳慶傑 On-Chip and Inter-Chip Bidirectional Transceivers |
| author_sort |
Ching-Chieh Wu |
| title |
On-Chip and Inter-Chip Bidirectional Transceivers |
| title_short |
On-Chip and Inter-Chip Bidirectional Transceivers |
| title_full |
On-Chip and Inter-Chip Bidirectional Transceivers |
| title_fullStr |
On-Chip and Inter-Chip Bidirectional Transceivers |
| title_full_unstemmed |
On-Chip and Inter-Chip Bidirectional Transceivers |
| title_sort |
on-chip and inter-chip bidirectional transceivers |
| publishDate |
2005 |
| url |
http://ndltd.ncl.edu.tw/handle/99279752450182947588 |
| work_keys_str_mv |
AT chingchiehwu onchipandinterchipbidirectionaltransceivers AT wúqìngjié onchipandinterchipbidirectionaltransceivers AT chingchiehwu jīngpiànshànghéjīngpiànjiānshuāngxiàngchuánshūjiēshōuqì AT wúqìngjié jīngpiànshànghéjīngpiànjiānshuāngxiàngchuánshūjiēshōuqì |
| _version_ |
1718298205325623296 |