The Investigation of Interfacial Reaction between Gold Stud Bump and Solder in Flip-Chip Chip Scale Package

• Main Authors: LI-JU HUANG, 黃麗如
• Other Authors: Tzu-Chen Hung
• Format: Others
• Language: zh-TW
• Published: 2005
• Online Access: http://ndltd.ncl.edu.tw/handle/35564230435829599819

碩士 === 義守大學 === 材料科學與工程學系 === 93 === This research has been conducted to investigate the variation of micro-structure due to the interfacial reaction between Gold Stud Bump and Sn63/Pb37 pre-solder substrate. After high temperature 150C storage test from 0 hour to 2000 hours, AuSn, AuSn2, and AuSn4 were detected in 0~100 hours period by EPMA. In early stage, Su and Au atoms were adequate. AuSn4 was the primary phase. To accompany interfacial reaction, Sn atoms depleted gradually. Then, AuSn4 phase transformed to AuSn and AuSn2 phases in 100 ~ 500 hours period. Finally, AuSn4 disappeared due to Sn atoms were exhausted. AuSn and AuSn2 were detected in 500~2000 hours period as well. The reacted phase layer thickness became thicker and thicker. Per cross section results, we do not see void and gold embitterment phenomenon of those samples. The Finite Element Method code, ANSYS, was adopted to simulate the warpage of FCCSP under thermal loading. The obtained results were compared with real product measurement and the trend of warpage is the same. The result reveals that the deflection is caused by the differences of material properties, as such solder, the maximum equivalent strain and stress of solder happens at the farthest of model where the destruction occurs most easily. Reliability test has being implemented by industry-wide for package assembly qualification. This kind of acceleration test was used to detect potential risk of design, material, and process in early stage. The result shows NCP with LCM method can pass JEDEC specification.