High Level Synthesis with Buffer Insertion
碩士 === 國立中興大學 === 資訊科學研究所 === 93 === In this paper, we propose three design techniques that link physical design problems to high-level synthesis. First, we provide an interconnect-aware resource allocation algorithm that minimizes total wire length in the high-level synthesis stage. Second, a floor...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2006
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| Online Access: | http://ndltd.ncl.edu.tw/handle/53132321750175229109 |