High Level Synthesis with Buffer Insertion

• Main Authors: Feng Ming Chang, 張峰銘
• Other Authors: Sying Jyan Wang
• Format: Others
• Language: zh-TW
• Published: 2006
• Online Access: http://ndltd.ncl.edu.tw/handle/53132321750175229109

碩士 === 國立中興大學 === 資訊科學研究所 === 93 === In this paper, we propose three design techniques that link physical design problems to high-level synthesis. First, we provide an interconnect-aware resource allocation algorithm that minimizes total wire length in the high-level synthesis stage. Second, a floorplanning method, which is based on the information obtained in high-level synthesis, is presented. Experimental results show that this approach achieves a 5% to 13% reduction in total wire length, compared with a commercial tool. Third, a fast clock-tree delay estimation algorithm, including buffer insertion, is used to estimate the clock-tree performance with respect to the given floorplan. Our experiments show that this estimation is very accurate. With this technique, interconnect structure that fails design constraints can be detected in early design cycle, and it may lead to a significant reduction in design time.