A 6-Bit Single Analog Path Flash ADC Operating at 2 GHz
碩士 === 國立成功大學 === 電機工程學系碩博士班 === 93 === Owing to the growing demand for GS/s level ADCs nowadays, a 6-bit single analog path 2 GS/s flash ADC is proposed in this thesis. This ADC is optimized to operate in high speed applications such as hard disk read channel and high speed communication system....
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/27210477379739401686 |