An Efficient Tile-Based ECO Router for SoC Designs
碩士 === 國立交通大學 === 資訊科學系所 === 93 === Remarkable advances in the process and circuit designs bring crucial challenges for optimizing the layout of a multi-million gate design. Moreover, introducing System On a Chip (SOC) design methodology greatly increases the design complexity and the layout integra...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82285947155170540687 |