An Efficient Tile-Based ECO Router for SoC Designs
碩士 === 國立交通大學 === 資訊科學系所 === 93 === Remarkable advances in the process and circuit designs bring crucial challenges for optimizing the layout of a multi-million gate design. Moreover, introducing System On a Chip (SOC) design methodology greatly increases the design complexity and the layout integra...
Main Authors: | Jian-Yin Li, 李建毅 |
---|---|
Other Authors: | Yih-Lang Li |
Format: | Others |
Language: | en_US |
Published: |
2005
|
Online Access: | http://ndltd.ncl.edu.tw/handle/82285947155170540687 |
Similar Items
-
Design of a crosspoint queued router for a micro-network in SoCs
by: Jhih-Sian Li, et al.
Published: (2010) -
An Efficient Tile-Based Router with Routing Graph Reduction
by: 陳文彬
Published: (2005) -
Design of Resource Control Hardware for SoC
by: Yun-LungLee, et al.
Published: (2015) -
An SoC Design Framework Integrating SDRAM Controller, SIPs, and SoC Bus Analyzer
by: Chun-Ching Wu, et al.
Published: (2009) -
Modified Booth Multiplier with BIST and Wrapper Design for SoC Application
by: JianHau Huang, et al.
Published: (2005)