High-Speed and Low-Power Multiplier-Accumulator Micro-Architecture and Circuit Design
碩士 === 國立交通大學 === 電子工程系所 === 93 === A power-speed optimization technique of circuit level for a datapath of processors is proposed in this thesis. By using efficient multiplication algorithms, a high-speed multiplier-accumulator micro-architecture is designed in this thesis. According to this high-s...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2004
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| Online Access: | http://ndltd.ncl.edu.tw/handle/68062221088208250298 |