On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction
碩士 === 國立交通大學 === 電子工程系所 === 93 === With the continuous shrinkage of device sizes, the global interconnect delay becomes a dominant factor of chip performance in deep-submicron technology. Furthermore, the signal propagation length in one clock cycle could be greatly reduced due to the strong induct...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/81051257321720055763 |