On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction

碩士 === 國立交通大學 === 電子工程系所 === 93 === With the continuous shrinkage of device sizes, the global interconnect delay becomes a dominant factor of chip performance in deep-submicron technology. Furthermore, the signal propagation length in one clock cycle could be greatly reduced due to the strong induct...

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Main Authors:	Jiun-Sheng Huang, 黃俊盛
Other Authors:	Jing-Yang Jou
Format:	Others
Language:	en_US
Published:	2005
Online Access:	http://ndltd.ncl.edu.tw/handle/81051257321720055763

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record_format	oai_dc
spelling	ndltd-TW-093NCTU54280152016-06-06T04:11:38Z http://ndltd.ncl.edu.tw/handle/81051257321720055763 On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction 針對晶片匯流排降低電感電容耦合效應之編碼技術 Jiun-Sheng Huang 黃俊盛碩士國立交通大學電子工程系所 93 With the continuous shrinkage of device sizes, the global interconnect delay becomes a dominant factor of chip performance in deep-submicron technology. Furthermore, the signal propagation length in one clock cycle could be greatly reduced due to the strong inductive and capacitive coupling effects on global interconnects. In order to reduce the coupling effects, many bus encoding methods have been proposed. However, most of them consider only resistance and capacitance effects. In this thesis, we propose a flexible bus encoding flow that can reduce the inductive and capacitive coupling delay on on-chip bus. In addition, combining with a curve fitting method, our encoding scheme can be utilized to increase the maximum propagation length in one clock cycle. Simulation results show that our flow can significantly reduce the inductance and capacitance coupling delay and, hence, increase the maximum propagation length of the given bus structure. Jing-Yang Jou 周景揚 2005 學位論文 ; thesis 64 en_US
collection	NDLTD
language	en_US
format	Others
sources	NDLTD
description	碩士 === 國立交通大學 === 電子工程系所 === 93 === With the continuous shrinkage of device sizes, the global interconnect delay becomes a dominant factor of chip performance in deep-submicron technology. Furthermore, the signal propagation length in one clock cycle could be greatly reduced due to the strong inductive and capacitive coupling effects on global interconnects. In order to reduce the coupling effects, many bus encoding methods have been proposed. However, most of them consider only resistance and capacitance effects. In this thesis, we propose a flexible bus encoding flow that can reduce the inductive and capacitive coupling delay on on-chip bus. In addition, combining with a curve fitting method, our encoding scheme can be utilized to increase the maximum propagation length in one clock cycle. Simulation results show that our flow can significantly reduce the inductance and capacitance coupling delay and, hence, increase the maximum propagation length of the given bus structure.
author2	Jing-Yang Jou
author_facet	Jing-Yang Jou Jiun-Sheng Huang 黃俊盛
author	Jiun-Sheng Huang 黃俊盛
spellingShingle	Jiun-Sheng Huang 黃俊盛 On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction
author_sort	Jiun-Sheng Huang
title	On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction
title_short	On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction
title_full	On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction
title_fullStr	On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction
title_full_unstemmed	On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction
title_sort	on-chip bus encoding for inductance and capacitance crosstalk reduction
publishDate	2005
url	http://ndltd.ncl.edu.tw/handle/81051257321720055763
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On-chip Bus Encoding for Inductance and Capacitance Crosstalk Reduction

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