| Summary: | 碩士 === 國立交通大學 === 電子工程系所 === 93 === A CMOS 5-bit 1GSamples/s flash analog-to-digital converter (ADC) implemented in 0.18-�慆 CMOS technology for low-power ultra-wideband (UWB) wireless applications is presented. A power-efficient architecture by combining the cascade resistive averaging and digital error correction technique is proposed. The principle of averaging technique and digital error correction is analyzed and discussed in detail. With the combining techniques, 85% power saving in preamplifiers is achieved and the power of 2N-1 pipeline latches is eliminated. The results show peak differential-nonlinearity (DNL) and integral-nonlinearity (INL) is less than 0.3LSB and 0.7LSB. The signal-to-noise-plus-distortion ratio (SNDR) at 2.9MHz is 30.5dB and the SNDR at 475MHz is 29dB. The total ADC including preamplifiers, comparators, clock buffers and digital error correction circuits consumes 86mW from 1.8V supply, leading to a figure of merit is merely 3.9pJ.
The measurement of the SNDR is 29dB under 800MHz sampling rate and 1.07MHz input frequency. The measured DNL and INL are +0.32/-0.22 LSB and +0.39/-0.24 LSB. The effective number of bits (ENOB) is calculated equal to 4.5 bits.
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