Low Power Floorplanning/Placement Methodology Considering Performance Constraints and Voltage Islands Generation
碩士 === 國立交通大學 === 電子工程系所 === 93 === Using voltage island methodology to reduce power consumption for System-on-a-Chip (SoC) designs becomes more and more popular recently. At present, this approach is mostly considered in system-level architecture. For hierarchical design and reuse intellectual prop...
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| Format: | Others |
| Language: | en_US |
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2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/yfjjb5 |