The Impact of Interfacial Layer and the Halo Implant on the Reliability of High K Dielectric CMOS Devices
碩士 === 國立交通大學 === 電子工程系所 === 93 === With the scaling of gate oxide thickness into 1 nm regime, the gate leakage current will increase exponentially with reducing thickness. Several different methods can be employed to improve device performance and reliability. Among them, high K gate stack CMOS dev...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/19384572148428672624 |