Extreme Voltage Stress Test of Analog/Mixed Signal ICs for Reliability Enhancement
碩士 === 國立中央大學 === 電機工程研究所 === 93 === The framework of extreme-voltage stress test system has been developed to reduce the lost yield caused by gate-oxide defects. However, the framework was developed for the gate-oxide defects that assume with 1/E model, where such a defect model is applicable for t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2005
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| Online Access: | http://ndltd.ncl.edu.tw/handle/67615990735943596106 |